1. Technical Field
The present invention relates generally to manufacturing processes, and more specifically relates to a system and method for optimizing a manufacturing process using partitioned process capability analysis.
2. Related Art
In complex manufacturing environments, such as semiconductor processing, it is often difficult to quantify the true capability of manufacturing processes or tools on a real time basis. Thus, it is often difficult to prospectively evaluate the efficacy of using a process or tool in a given way. For instance, in a semiconductor fabrication process, it is often desirable to take sample measurements (i.e., metrology sampling) from a “lot” of wafers when measuring overlay and the like to ensure high performance. A typical lot comprises about 20 silicon wafers. However, metrology adds a significant cost to the overall process. Accordingly, to the extent “skip lot sampling” can be implemented to eliminate metrology sampling, the cost of the overall fabrication process can be lowered. Other aspects of wafer processing include the requirement to select a tool to deploy product for the particular operation. Determining which tool will provide the best balance of performance and cost effectiveness is critical in achieving overall manufacturing efficiencies.
Existing techniques for analyzing capability generally involve reviewing data collected from previous manufacturing operations. Statistical Process Control (SPC) is often used as the mechanism for monitoring changes in capability. However, techniques such as SPC generate prohibitively large amounts of data. The volume of data results in slow reactions to change, and is difficult to use for troubleshooting. Often, the SPC charts do not provide a detailed understanding of the interactions inherent in the process controls.
For instance, skip lot sampling plans, which dictate when the metrology step can be skipped for a specific lot, are often determined based on process capability analysis (Cpk) calculations of very broadly generalized datasets such as technology and level combinations. Unfortunately, such calculations are typically made on an infrequent basis and are typically not revisited for significant periods of time. Thus, the capability analysis reacts very slowly, or not at all, to performance improvements or degradations. Capability analysis systems are, for example, described in U.S. Patent Application U.S. 2002/0026257 A1, published on Feb. 28, 2002 by Newmark, entitled “Capability Analysis of Assembly Line Production,” which is hereby incorporated by reference.
Moreover, due to the need to simplify SPC charting, data related to many technologies and levels are often combined in the same analysis. Capability analysis of the combined data hides the individual capabilities of specific tools, reticles, part numbers, etc., and results in missed optimizations. For instance, a targeted subset of the data may indicate a low risk opportunity to skip metrology for a lot of wafers under a given set of circumstances, which may be missed since the data could only be analyzed at a very high level. Similar misleading results could also impact tool deployment, which is historically based on a tool capability analysis